A PCB-Embedded 1.2 kV SiC MOSFET Package With Reduced Manufacturing Complexity
This article presents a printed circuit board (PCB) -embedded 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) half-bridge package for a 22 kW electric vehicle (EV) on-board charger (OBC). The package meets the application's thermal and electrical re...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2023-01-01
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| Series: | IEEE Open Journal of Power Electronics |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10176350/ |
| _version_ | 1827897977070419968 |
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| author | Jack Knoll Christina DiMarino Hannes Stahr Mike Morianz |
| author_facet | Jack Knoll Christina DiMarino Hannes Stahr Mike Morianz |
| author_sort | Jack Knoll |
| collection | DOAJ |
| description | This article presents a printed circuit board (PCB) -embedded 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) half-bridge package for a 22 kW electric vehicle (EV) on-board charger (OBC). The package meets the application's thermal and electrical requirements while eliminating or reducing factors that drive up manufacturing complexity and footprint in PCBs. Factors such as integration necessity, trace width, and layer count are considered. The package has been prototyped and subjected to electrical and thermal characterization. Static characterization performed on the package prototypes has revealed that the package contributes approximately 0.4 mΩ of parasitic resistance to the power loop. The simulated minimum power-loop and gate-loop inductances of the final package are 2.4 nH and 1.6 nH, respectively. Double pulse tests (DPTs) performed on the final package at 800 V and 25 A revealed that the low loop inductances allow the high-side and low-side switches to achieve 41 V/ns and 37 V/ns turn-off <italic>dv/dts</italic>, respectively, with drain-to-source voltage (V<sub>DS</sub>) overshoots of 34 V and 30 V, respectively. The selection of a non-isolated case, along with other design choices, has helped limit the junction-to-case thermal resistance (R<sub>TH,JC</sub>) of each MOSFET to 0.074 K/W. |
| first_indexed | 2024-03-12T22:57:22Z |
| format | Article |
| id | doaj.art-ec5a5f477f944457bfea01e6253320e4 |
| institution | Directory Open Access Journal |
| issn | 2644-1314 |
| language | English |
| last_indexed | 2024-03-12T22:57:22Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of Power Electronics |
| spelling | doaj.art-ec5a5f477f944457bfea01e6253320e42023-07-19T23:00:58ZengIEEEIEEE Open Journal of Power Electronics2644-13142023-01-01454956010.1109/OJPEL.2023.329372910176350A PCB-Embedded 1.2 kV SiC MOSFET Package With Reduced Manufacturing ComplexityJack Knoll0https://orcid.org/0000-0002-7864-1719Christina DiMarino1https://orcid.org/0000-0001-7369-649XHannes Stahr2Mike Morianz3Center for Power Electronics Systems, Virginia Polytechnic Institute and State University, Blacksburg, VA, USACenter for Power Electronics Systems, Virginia Polytechnic Institute and State University, Blacksburg, VA, USAAustria Technologie and Systmetechnik AG (AT&S), Leoben, AustriaAustria Technologie and Systmetechnik AG (AT&S), Leoben, AustriaThis article presents a printed circuit board (PCB) -embedded 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) half-bridge package for a 22 kW electric vehicle (EV) on-board charger (OBC). The package meets the application's thermal and electrical requirements while eliminating or reducing factors that drive up manufacturing complexity and footprint in PCBs. Factors such as integration necessity, trace width, and layer count are considered. The package has been prototyped and subjected to electrical and thermal characterization. Static characterization performed on the package prototypes has revealed that the package contributes approximately 0.4 mΩ of parasitic resistance to the power loop. The simulated minimum power-loop and gate-loop inductances of the final package are 2.4 nH and 1.6 nH, respectively. Double pulse tests (DPTs) performed on the final package at 800 V and 25 A revealed that the low loop inductances allow the high-side and low-side switches to achieve 41 V/ns and 37 V/ns turn-off <italic>dv/dts</italic>, respectively, with drain-to-source voltage (V<sub>DS</sub>) overshoots of 34 V and 30 V, respectively. The selection of a non-isolated case, along with other design choices, has helped limit the junction-to-case thermal resistance (R<sub>TH,JC</sub>) of each MOSFET to 0.074 K/W.https://ieeexplore.ieee.org/document/10176350/Electric vehicleintegrationon-board chargerpackagingPCB embeddingSiC MOSFET |
| spellingShingle | Jack Knoll Christina DiMarino Hannes Stahr Mike Morianz A PCB-Embedded 1.2 kV SiC MOSFET Package With Reduced Manufacturing Complexity IEEE Open Journal of Power Electronics Electric vehicle integration on-board charger packaging PCB embedding SiC MOSFET |
| title | A PCB-Embedded 1.2 kV SiC MOSFET Package With Reduced Manufacturing Complexity |
| title_full | A PCB-Embedded 1.2 kV SiC MOSFET Package With Reduced Manufacturing Complexity |
| title_fullStr | A PCB-Embedded 1.2 kV SiC MOSFET Package With Reduced Manufacturing Complexity |
| title_full_unstemmed | A PCB-Embedded 1.2 kV SiC MOSFET Package With Reduced Manufacturing Complexity |
| title_short | A PCB-Embedded 1.2 kV SiC MOSFET Package With Reduced Manufacturing Complexity |
| title_sort | pcb embedded 1 2 kv sic mosfet package with reduced manufacturing complexity |
| topic | Electric vehicle integration on-board charger packaging PCB embedding SiC MOSFET |
| url | https://ieeexplore.ieee.org/document/10176350/ |
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