Optimal inverter logic gate using 10-nm double gate-all-around (DGAA) transistor with asymmetric channel width
We investigate the electrical characteristics of a double-gate-all-around (DGAA) transistor with an asymmetric channel width using three-dimensional device simulation. The DGAA structure creates a silicon nanotube field-effect transistor (NTFET) with a core-shell gate architecture, which can solve t...
Main Authors: | , , |
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Format: | Article |
Language: | English |
Published: |
AIP Publishing LLC
2016-01-01
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Series: | AIP Advances |
Online Access: | http://dx.doi.org/10.1063/1.4940755 |