Evaluation of the soft error assessment consistency of a JIT‐based virtual platform simulator

Evaluation of the soft error assessment consistency of a JIT‐based virtual platform simulator

Abstract Soft error resilience has become an essential design metric in electronic computing systems as advanced technology nodes have become less robust to high‐charged particle effects. Designers, therefore, should be able to assess this metric considering several software stack components running...

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Bibliographic Details
Main Authors: Geancarlo Abich, Rafael Garibotti, Vitor Bandeira, Felipe da Rosa, Jonas Gava, Felipe Bortolon, Guilherme Medeiros, Fernando G. Moraes, Ricardo Reis, Luciano Ost
Format: Article
Language:English
Published: Hindawi-IET 2021-03-01
Series:IET Computers & Digital Techniques
Subjects:
program compilers
just‐in‐time
microprocessor chips
radiation hardening (electronics)
Linux
multiprocessing systems
Online Access:https://doi.org/10.1049/cdt2.12017

Internet

https://doi.org/10.1049/cdt2.12017

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