Consideration of UFET Architecture for the 5 nm Node and Beyond Logic Transistor
In this paper, we propose a trench MOS architecture for the upcoming 5 nm node and beyond logic transistor. The intended device has a gate formed vertically downward, with added spacers along the gate to S/D sidewall. In doing so, the recessed device having longer channel length (than the defined ga...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2018-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/8466575/ |