Improving the LUT Count for Mealy FSMS with Transformation of Output Collections

Improving the LUT Count for Mealy FSMS with Transformation of Output Collections

A method is proposed which aims at reducing the number of LUTs in the circuits of FPGA-based Mealy finite state machines (FSMs) with transformation of collections of outputs into state codes. The reduction is achieved due to the use of two-component state codes. Such an approach allows reducing the...

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Bibliographic Details
Main Authors: Barkalov Alexander, Titarenko Larysa, Mazurkiewicz Małgorzata
Format: Article
Language:English
Published: Sciendo 2022-09-01
Series:International Journal of Applied Mathematics and Computer Science
Subjects:
mealy fsm
fpga
lut
synthesis
state codes
Online Access:https://doi.org/10.34768/amcs-2022-0035

Internet

https://doi.org/10.34768/amcs-2022-0035

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