Exploring Adaptive Cache for Reconfigurable VLIW Processor
In this paper, we focus on a very long instruction word (VLIW) processor design that “shares” its cache blocks when switching to different performance modes to alleviate the aforementioned cold starts. The switching trigger cache resizing operations and improper use can lead to...
| Váldodahkkit: | , |
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| Materiálatiipa: | Artihkal |
| Giella: | English |
| Almmustuhtton: |
IEEE
2019-01-01
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| Ráidu: | IEEE Access |
| Fáttát: | |
| Liŋkkat: | https://ieeexplore.ieee.org/document/8725889/ |