Synthesis of FPGA architectures of block lifting-based filter banks in quaternion algebra (part 2)
Nowadays the methodology for designing systems on a chip is based on highly parameterized IP (itellectual property) components which provide a wide range of adjustment of resources, fixed point arithmetic data formats, and system performance for a specific application. The article desc...
| Main Authors: | , |
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| Format: | Article |
| Language: | Russian |
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The United Institute of Informatics Problems of the National Academy of Sciences of Belarus
2018-09-01
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| Series: | Informatika |
| Subjects: | |
| Online Access: | https://inf.grid.by/jour/article/view/422 |
| _version_ | 1797877347230154752 |
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| author | E. V. Rybenkov N. A. Petrovsky |
| author_facet | E. V. Rybenkov N. A. Petrovsky |
| author_sort | E. V. Rybenkov |
| collection | DOAJ |
| description | Nowadays the methodology for designing systems on a chip is based on highly parameterized IP (itellectual property) components which provide a wide range of adjustment of resources, fixed point arithmetic data formats, and system performance for a specific application. The article describes a flexible technology for rapid prototyping of processor architectures for integer, invertible, paraunitary filter banks in quaternion algebra (Int-Q-PUFB) based on the FPGA Q-MUL IP-component as multiplication operator for quaternions on distributed arithmetic on adders. Implementation of Int-Q-PUFB on FPGA Xilinx Zynq 7010, with 8-channel 8x24 Int-Q-PUFB has a perfect reconstruction property of the input data for a fixed point format, small hardware resource utilization and a slight delay in the pipeline compared to the known solutions for CORDIC-processors and distributed arithmetic on the memory. |
| first_indexed | 2024-04-10T02:15:42Z |
| format | Article |
| id | doaj.art-f149d363ef7e4f63ac03df1b1b563747 |
| institution | Directory Open Access Journal |
| issn | 1816-0301 |
| language | Russian |
| last_indexed | 2024-04-10T02:15:42Z |
| publishDate | 2018-09-01 |
| publisher | The United Institute of Informatics Problems of the National Academy of Sciences of Belarus |
| record_format | Article |
| series | Informatika |
| spelling | doaj.art-f149d363ef7e4f63ac03df1b1b5637472023-03-13T08:32:20ZrusThe United Institute of Informatics Problems of the National Academy of Sciences of BelarusInformatika1816-03012018-09-011532231411Synthesis of FPGA architectures of block lifting-based filter banks in quaternion algebra (part 2)E. V. Rybenkov0N. A. Petrovsky1Belarusian State University of Informatics and RadioelectronicsBelarusian State University of Informatics and RadioelectronicsNowadays the methodology for designing systems on a chip is based on highly parameterized IP (itellectual property) components which provide a wide range of adjustment of resources, fixed point arithmetic data formats, and system performance for a specific application. The article describes a flexible technology for rapid prototyping of processor architectures for integer, invertible, paraunitary filter banks in quaternion algebra (Int-Q-PUFB) based on the FPGA Q-MUL IP-component as multiplication operator for quaternions on distributed arithmetic on adders. Implementation of Int-Q-PUFB on FPGA Xilinx Zynq 7010, with 8-channel 8x24 Int-Q-PUFB has a perfect reconstruction property of the input data for a fixed point format, small hardware resource utilization and a slight delay in the pipeline compared to the known solutions for CORDIC-processors and distributed arithmetic on the memory.https://inf.grid.by/jour/article/view/422lossless-to-lossyquaternionsimage compressionfpgafilter bankblock-lifting factorization |
| spellingShingle | E. V. Rybenkov N. A. Petrovsky Synthesis of FPGA architectures of block lifting-based filter banks in quaternion algebra (part 2) Informatika lossless-to-lossy quaternions image compression fpga filter bank block-lifting factorization |
| title | Synthesis of FPGA architectures of block lifting-based filter banks in quaternion algebra (part 2) |
| title_full | Synthesis of FPGA architectures of block lifting-based filter banks in quaternion algebra (part 2) |
| title_fullStr | Synthesis of FPGA architectures of block lifting-based filter banks in quaternion algebra (part 2) |
| title_full_unstemmed | Synthesis of FPGA architectures of block lifting-based filter banks in quaternion algebra (part 2) |
| title_short | Synthesis of FPGA architectures of block lifting-based filter banks in quaternion algebra (part 2) |
| title_sort | synthesis of fpga architectures of block lifting based filter banks in quaternion algebra part 2 |
| topic | lossless-to-lossy quaternions image compression fpga filter bank block-lifting factorization |
| url | https://inf.grid.by/jour/article/view/422 |
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