Capacitance Multiplier Using Small Values of Multiplication Factors for Adjustability Extension and Parasitic Resistance Cancellation Technique

This paper presents a new concept of a capacitance multiplier using the topology of differential voltage buffer and current conveyor, where the capacitor is connected to the current input terminal. The presented topology overcomes the typical issue known from similar solutions, i.e. creation of an u...

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Bibliographic Details
Main Authors: Roman Sotner, Jan Jerabek, Ladislav Polak, Jiri Petrzela
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Access
Subjects:
Online Access:https://ieeexplore.ieee.org/document/9159558/