A Novel Planar Architecture for Heterojunction TFETs With Improved Performance and Its Digital Application as an Inverter
A novel planar architecture is proposed for tunnel field-effect transistors (TFETs). The advantages of this architecture are exhibited, taking the InAs/Si TFET as an example, and the effects of different device parameters are analyzed in detail. Owing to the gate field being parallel to the tunnelin...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2020-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/8976103/ |