A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device
In this work, the effects of the mini-local oxidation of silicon (LOCOS) field plate’s bottom physical profile on the devices’ breakdown performance are analyzed through technology computer-aided design simulations. It is indicated that the “abrupt” bottom profile could certainly do with an optimiza...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi-IET
2023-01-01
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| Series: | IET Circuits, Devices and Systems |
| Online Access: | http://dx.doi.org/10.1049/2023/5298361 |