High-Throughput Low Power Area Efficient 17-bit 2’s Complement Multilayer Perceptron Components and Architecture for on-Chip Machine Learning in Implantable Devices

High-Throughput Low Power Area Efficient 17-bit 2’s Complement Multilayer Perceptron Components and Architecture for on-Chip Machine Learning in Implantable Devices

In this manuscript the authors, design new hardware efficient combinational building blocks for a Multi Layer Perceptron (MLP) unit which eliminates the need for hardware generic Digital Signal Processing (DSP) units and also eliminates the need for on-chip block RAMs (BRAMs). The components were de...

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Bibliographic Details
Main Authors: Brian James Romaine, Mario Pereira Martin
Format: Article
Language:English
Published: IEEE 2022-01-01
Series:IEEE Access
Subjects:
Low power
area optimization
integrated circuits
FPGA
neural networks
perceptron
Online Access:https://ieeexplore.ieee.org/document/9870814/

Internet

https://ieeexplore.ieee.org/document/9870814/

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