A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology
A novice advanced architecture of 8-bit analog to digital converter is introduced and analyzed in this paper. The structure of proposed ADC is based on the sub-ranging ADC architecture in which a 4-bit resolution flash-ADC is utilized. The proposed ADC architecture is designed by employing a compara...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Polish Academy of Sciences
2021-09-01
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| Series: | International Journal of Electronics and Telecommunications |
| Subjects: | |
| Online Access: | https://journals.pan.pl/Content/118908/PDF/50_2917_Khatak_skl.pdf |