A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs
This paper proposes a resolution control loop that runs in background to control the time resolution of a mid-rise Time to Digital Converter (TDC) used as a phase detector in All-Digital Phase Locked Loops (ADPLLs). The proposed resolution control loop minimizes the TDC resolution until the TDC line...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2023-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10097748/ |