A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs
This paper proposes a resolution control loop that runs in background to control the time resolution of a mid-rise Time to Digital Converter (TDC) used as a phase detector in All-Digital Phase Locked Loops (ADPLLs). The proposed resolution control loop minimizes the TDC resolution until the TDC line...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2023-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10097748/ |
| _version_ | 1827964800906297344 |
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| author | Abdelrahman Habib Mohamed Dessouky Ahmed Naguib |
| author_facet | Abdelrahman Habib Mohamed Dessouky Ahmed Naguib |
| author_sort | Abdelrahman Habib |
| collection | DOAJ |
| description | This paper proposes a resolution control loop that runs in background to control the time resolution of a mid-rise Time to Digital Converter (TDC) used as a phase detector in All-Digital Phase Locked Loops (ADPLLs). The proposed resolution control loop minimizes the TDC resolution until the TDC linear dynamic range equals the range of the input time error. Consequently, PLL in-band phase noise is reduced due to reduction of the Power Spectral Density (PSD) of the TDC quantization noise. Moreover, the linearity of the TDC transfer function across the range of the input time error is guaranteed. On contrary, the counterpart resolution control loop based on Lloyd-Max algorithm does not guarantee the linearity of the TDC transfer function across the range of the input time error. Furthermore, the proposed resolution control loop achieves TDC quantization noise with a lower variance compared to that achieved by the counterpart resolution control loop when applied with a TDC with more than 3 bits. Finally, the hardware implementation of the proposed resolution control loop is more area and power efficient compared to the implementation of the counterpart resolution control loop. |
| first_indexed | 2024-04-09T17:22:15Z |
| format | Article |
| id | doaj.art-fb50ee58adcb4f7e9404f291898b5023 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-09T17:22:15Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-fb50ee58adcb4f7e9404f291898b50232023-04-18T23:00:20ZengIEEEIEEE Access2169-35362023-01-0111360733608110.1109/ACCESS.2023.326572610097748A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLsAbdelrahman Habib0https://orcid.org/0000-0001-9382-8234Mohamed Dessouky1https://orcid.org/0000-0003-3829-6284Ahmed Naguib2Electronics and Electrical Communications Engineering Department, Faculty of Engineering, Ain Shams University, Cairo, EgyptElectronics and Electrical Communications Engineering Department, Faculty of Engineering, Ain Shams University, Cairo, EgyptElectronic Engineering Department, Military Technical College, Cairo, EgyptThis paper proposes a resolution control loop that runs in background to control the time resolution of a mid-rise Time to Digital Converter (TDC) used as a phase detector in All-Digital Phase Locked Loops (ADPLLs). The proposed resolution control loop minimizes the TDC resolution until the TDC linear dynamic range equals the range of the input time error. Consequently, PLL in-band phase noise is reduced due to reduction of the Power Spectral Density (PSD) of the TDC quantization noise. Moreover, the linearity of the TDC transfer function across the range of the input time error is guaranteed. On contrary, the counterpart resolution control loop based on Lloyd-Max algorithm does not guarantee the linearity of the TDC transfer function across the range of the input time error. Furthermore, the proposed resolution control loop achieves TDC quantization noise with a lower variance compared to that achieved by the counterpart resolution control loop when applied with a TDC with more than 3 bits. Finally, the hardware implementation of the proposed resolution control loop is more area and power efficient compared to the implementation of the counterpart resolution control loop.https://ieeexplore.ieee.org/document/10097748/All-digital phase locked loops (ADPLLs)time to digital converter (TDC)bang-bang phase detector (BBPD)bang-bang phase locked loop (BBPLL)digital loop filter (DLF)digital controlled oscillator (DCO) |
| spellingShingle | Abdelrahman Habib Mohamed Dessouky Ahmed Naguib A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs IEEE Access All-digital phase locked loops (ADPLLs) time to digital converter (TDC) bang-bang phase detector (BBPD) bang-bang phase locked loop (BBPLL) digital loop filter (DLF) digital controlled oscillator (DCO) |
| title | A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs |
| title_full | A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs |
| title_fullStr | A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs |
| title_full_unstemmed | A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs |
| title_short | A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs |
| title_sort | resolution control loop for tdc based phase detectors in adplls |
| topic | All-digital phase locked loops (ADPLLs) time to digital converter (TDC) bang-bang phase detector (BBPD) bang-bang phase locked loop (BBPLL) digital loop filter (DLF) digital controlled oscillator (DCO) |
| url | https://ieeexplore.ieee.org/document/10097748/ |
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