1T Capacitor-Less DRAM Cell Based on Asymmetric Tunnel FET Design
In this work we propose and demonstrate the use of a Tunnel FET (TFET) as capacitorless DRAM cell based on TCAD simulations and experiments. We report more experimental results on Tunnel FETs implemented as a double-gate (DG) fully-depleted Silicon-On-Insulator (FD-SOI) devices. The Tunnel FET based...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2015-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/6990484/ |