1T Capacitor-Less DRAM Cell Based on Asymmetric Tunnel FET Design
In this work we propose and demonstrate the use of a Tunnel FET (TFET) as capacitorless DRAM cell based on TCAD simulations and experiments. We report more experimental results on Tunnel FETs implemented as a double-gate (DG) fully-depleted Silicon-On-Insulator (FD-SOI) devices. The Tunnel FET based...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2015-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/6990484/ |
| _version_ | 1818419638117072896 |
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| author | Arnab Biswas Adrian M. Ionescu |
| author_facet | Arnab Biswas Adrian M. Ionescu |
| author_sort | Arnab Biswas |
| collection | DOAJ |
| description | In this work we propose and demonstrate the use of a Tunnel FET (TFET) as capacitorless DRAM cell based on TCAD simulations and experiments. We report more experimental results on Tunnel FETs implemented as a double-gate (DG) fully-depleted Silicon-On-Insulator (FD-SOI) devices. The Tunnel FET based DRAM cell has an asymmetric body and a partial overlap of the top gate (L<sub>G1</sub>) with a total overlap of the back gate over the channel region (L<sub>G2</sub>). A potential well is created by biasing the back gate (V<sub>G2</sub>) in accumulation while the front gate (V<sub>G1</sub>) is in inversion. Holes from the p+ source are injected by the forward-biased source/channel junction and stored in the electrically induced potential well. Programming conditions and related transients are reported and the role of temperature is investigated. |
| first_indexed | 2024-12-14T12:41:45Z |
| format | Article |
| id | doaj.art-fbeddc7871ef4b11afcd34e408f61a23 |
| institution | Directory Open Access Journal |
| issn | 2168-6734 |
| language | English |
| last_indexed | 2024-12-14T12:41:45Z |
| publishDate | 2015-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj.art-fbeddc7871ef4b11afcd34e408f61a232022-12-21T23:00:54ZengIEEEIEEE Journal of the Electron Devices Society2168-67342015-01-013321722210.1109/JEDS.2014.238275969904841T Capacitor-Less DRAM Cell Based on Asymmetric Tunnel FET DesignArnab Biswas0Adrian M. Ionescu1Nanolab, Ecole Polytechnique Fédérale de Lausanne, Lausanne, SwitzerlandNanolab, Ecole Polytechnique Fédérale de Lausanne, Lausanne, SwitzerlandIn this work we propose and demonstrate the use of a Tunnel FET (TFET) as capacitorless DRAM cell based on TCAD simulations and experiments. We report more experimental results on Tunnel FETs implemented as a double-gate (DG) fully-depleted Silicon-On-Insulator (FD-SOI) devices. The Tunnel FET based DRAM cell has an asymmetric body and a partial overlap of the top gate (L<sub>G1</sub>) with a total overlap of the back gate over the channel region (L<sub>G2</sub>). A potential well is created by biasing the back gate (V<sub>G2</sub>) in accumulation while the front gate (V<sub>G1</sub>) is in inversion. Holes from the p+ source are injected by the forward-biased source/channel junction and stored in the electrically induced potential well. Programming conditions and related transients are reported and the role of temperature is investigated.https://ieeexplore.ieee.org/document/6990484/Tunnel FETDRAMCapacitorless memory1T/0C |
| spellingShingle | Arnab Biswas Adrian M. Ionescu 1T Capacitor-Less DRAM Cell Based on Asymmetric Tunnel FET Design IEEE Journal of the Electron Devices Society Tunnel FET DRAM Capacitorless memory 1T/0C |
| title | 1T Capacitor-Less DRAM Cell Based on Asymmetric Tunnel FET Design |
| title_full | 1T Capacitor-Less DRAM Cell Based on Asymmetric Tunnel FET Design |
| title_fullStr | 1T Capacitor-Less DRAM Cell Based on Asymmetric Tunnel FET Design |
| title_full_unstemmed | 1T Capacitor-Less DRAM Cell Based on Asymmetric Tunnel FET Design |
| title_short | 1T Capacitor-Less DRAM Cell Based on Asymmetric Tunnel FET Design |
| title_sort | 1t capacitor less dram cell based on asymmetric tunnel fet design |
| topic | Tunnel FET DRAM Capacitorless memory 1T/0C |
| url | https://ieeexplore.ieee.org/document/6990484/ |
| work_keys_str_mv | AT arnabbiswas 1tcapacitorlessdramcellbasedonasymmetrictunnelfetdesign AT adrianmionescu 1tcapacitorlessdramcellbasedonasymmetrictunnelfetdesign |