An 8-bit TDC implemented with two nested Johnson counters

An 8-bit TDC implemented with two nested Johnson counters

This work presents a Time-to-Digital Converter implemented using two nested Johnson counters and suitable for time-lapse measurement applications. The proposed structure is composed of two 4-bit nested counters, two digital-logic control networks, two registers and a single decoder. Semi-dynamic lo...

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Bibliographic Details
Main Authors: Jonathan Santiago-Fernandez, Alejandro Diaz-Sanchez, Gregorio Zamora-Mejia, Jose Miguel Rocha-Perez
Format: Article
Language:Spanish
Published: Instituto Tecnológico de Costa Rica 2023-06-01
Series:Tecnología en Marcha
Subjects:
TDC
Jonhson counter
semi-dynamic logic
nested counters
time-lapse measurement
time-todigital converter
Online Access:https://172.20.14.50/index.php/tec_marcha/article/view/6769

Internet

https://172.20.14.50/index.php/tec_marcha/article/view/6769

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