An 8-bit TDC implemented with two nested Johnson counters
This work presents a Time-to-Digital Converter implemented using two nested Johnson counters and suitable for time-lapse measurement applications. The proposed structure is composed of two 4-bit nested counters, two digital-logic control networks, two registers and a single decoder. Semi-dynamic lo...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | Spanish |
| Published: |
Instituto Tecnológico de Costa Rica
2023-06-01
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| Series: | Tecnología en Marcha |
| Subjects: | |
| Online Access: | https://172.20.14.50/index.php/tec_marcha/article/view/6769 |
| _version_ | 1827786684720218112 |
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| author | Jonathan Santiago-Fernandez Alejandro Diaz-Sanchez Gregorio Zamora-Mejia Jose Miguel Rocha-Perez |
| author_facet | Jonathan Santiago-Fernandez Alejandro Diaz-Sanchez Gregorio Zamora-Mejia Jose Miguel Rocha-Perez |
| author_sort | Jonathan Santiago-Fernandez |
| collection | DOAJ |
| description |
This work presents a Time-to-Digital Converter implemented using two nested Johnson counters and suitable for time-lapse measurement applications. The proposed structure is composed of two 4-bit nested counters, two digital-logic control networks, two registers and a single decoder. Semi-dynamic logic was used for the decoder to reduce its power consumption. The system has a standard digital output and is powered by a 1.8 V supply with a total power consumption of 32.4 mW. A prototype was fabricated using a TSMC 180 nm CMOS technology. The proposed structure uses a 508 µm x 225 µm area. In addition, this TDC has a standard deviation of 0.78 LSB with a fixed input time interval operating at a frequency of 1 MHz. The proposed structure shows good performance results and repeatability for continuous conversion conditions, these results are attributed to the simplicity of the system and the use of counters with minimum gate delay as the main elements for the TDC.
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| first_indexed | 2024-03-11T16:37:41Z |
| format | Article |
| id | doaj.art-fe02172fe08642c2928a2991a969eae7 |
| institution | Directory Open Access Journal |
| issn | 0379-3982 2215-3241 |
| language | Spanish |
| last_indexed | 2024-03-11T16:37:41Z |
| publishDate | 2023-06-01 |
| publisher | Instituto Tecnológico de Costa Rica |
| record_format | Article |
| series | Tecnología en Marcha |
| spelling | doaj.art-fe02172fe08642c2928a2991a969eae72023-10-23T14:26:51ZspaInstituto Tecnológico de Costa RicaTecnología en Marcha0379-39822215-32412023-06-0136610.18845/tm.v36i6.6769An 8-bit TDC implemented with two nested Johnson countersJonathan Santiago-FernandezAlejandro Diaz-SanchezGregorio Zamora-MejiaJose Miguel Rocha-Perez This work presents a Time-to-Digital Converter implemented using two nested Johnson counters and suitable for time-lapse measurement applications. The proposed structure is composed of two 4-bit nested counters, two digital-logic control networks, two registers and a single decoder. Semi-dynamic logic was used for the decoder to reduce its power consumption. The system has a standard digital output and is powered by a 1.8 V supply with a total power consumption of 32.4 mW. A prototype was fabricated using a TSMC 180 nm CMOS technology. The proposed structure uses a 508 µm x 225 µm area. In addition, this TDC has a standard deviation of 0.78 LSB with a fixed input time interval operating at a frequency of 1 MHz. The proposed structure shows good performance results and repeatability for continuous conversion conditions, these results are attributed to the simplicity of the system and the use of counters with minimum gate delay as the main elements for the TDC. https://172.20.14.50/index.php/tec_marcha/article/view/6769TDCJonhson countersemi-dynamic logicnested counterstime-lapse measurementtime-todigital converter |
| spellingShingle | Jonathan Santiago-Fernandez Alejandro Diaz-Sanchez Gregorio Zamora-Mejia Jose Miguel Rocha-Perez An 8-bit TDC implemented with two nested Johnson counters Tecnología en Marcha TDC Jonhson counter semi-dynamic logic nested counters time-lapse measurement time-todigital converter |
| title | An 8-bit TDC implemented with two nested Johnson counters |
| title_full | An 8-bit TDC implemented with two nested Johnson counters |
| title_fullStr | An 8-bit TDC implemented with two nested Johnson counters |
| title_full_unstemmed | An 8-bit TDC implemented with two nested Johnson counters |
| title_short | An 8-bit TDC implemented with two nested Johnson counters |
| title_sort | 8 bit tdc implemented with two nested johnson counters |
| topic | TDC Jonhson counter semi-dynamic logic nested counters time-lapse measurement time-todigital converter |
| url | https://172.20.14.50/index.php/tec_marcha/article/view/6769 |
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