Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models
Cryogenic CMOS is a crucial component in building scalable quantum computers, predominantly for interface and control circuitry. Further, high-performance computing can also benefit from cryogenic boosters. This necessitates an in-depth understanding of the power and performance trade-offs in the cr...
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| Format: | Article |
| Language: | English |
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IEEE
2021-01-01
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| Series: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9627705/ |
| _version_ | 1828127185852956672 |
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| author | Rakshith Saligram Wriddhi Chakraborty Ningyuan Cao Yu Cao Suman Datta Arijit Raychowdhury |
| author_facet | Rakshith Saligram Wriddhi Chakraborty Ningyuan Cao Yu Cao Suman Datta Arijit Raychowdhury |
| author_sort | Rakshith Saligram |
| collection | DOAJ |
| description | Cryogenic CMOS is a crucial component in building scalable quantum computers, predominantly for interface and control circuitry. Further, high-performance computing can also benefit from cryogenic boosters. This necessitates an in-depth understanding of the power and performance trade-offs in the cryogenic operation of digital logic. In this article, we analyze digital standard cells in a 28 nm high-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> metal gate (HKMG) CMOS foundry process design kit (PDK). We have developed Berkeley Short-channel IGFET Model (BSIM)4 of cryogenic CMOS and calibrated them with experimental measurements. Since low-temperature operation leads to an exponential decrease in the leakage current of the transistors, we further tune the threshold voltage of the devices to achieve iso-leakage. In this article, we present inverter static and dynamic characteristics and multiple ring oscillator (RO) structures. The simulation study shows that we can achieve 28% (FO4-RO) – 59% (NAND3-RO) higher performance under iso-<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {DD}}$ </tex-math></inline-formula> scenario and up to 90% improvement in the energy-delay product (EDP) under iso-overdrive scenario at 6 K compared to room temperature. |
| first_indexed | 2024-04-11T15:46:25Z |
| format | Article |
| id | doaj.art-ffffef510dde49f39a1576d177dfb67d |
| institution | Directory Open Access Journal |
| issn | 2329-9231 |
| language | English |
| last_indexed | 2024-04-11T15:46:25Z |
| publishDate | 2021-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| spelling | doaj.art-ffffef510dde49f39a1576d177dfb67d2022-12-22T04:15:31ZengIEEEIEEE Journal on Exploratory Solid-State Computational Devices and Circuits2329-92312021-01-017219320010.1109/JXCDC.2021.31311009627705Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM ModelsRakshith Saligram0https://orcid.org/0000-0002-7436-9375Wriddhi Chakraborty1https://orcid.org/0000-0003-3682-2420Ningyuan Cao2Yu Cao3https://orcid.org/0000-0001-6968-1180Suman Datta4https://orcid.org/0000-0001-6044-5173Arijit Raychowdhury5https://orcid.org/0000-0001-8391-0576School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USADepartment of Electrical Engineering, University of Notre Dame, Notre Dame, IN, USADepartment of Electrical Engineering, University of Notre Dame, Notre Dame, IN, USASchool of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USADepartment of Electrical Engineering, University of Notre Dame, Notre Dame, IN, USASchool of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USACryogenic CMOS is a crucial component in building scalable quantum computers, predominantly for interface and control circuitry. Further, high-performance computing can also benefit from cryogenic boosters. This necessitates an in-depth understanding of the power and performance trade-offs in the cryogenic operation of digital logic. In this article, we analyze digital standard cells in a 28 nm high-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> metal gate (HKMG) CMOS foundry process design kit (PDK). We have developed Berkeley Short-channel IGFET Model (BSIM)4 of cryogenic CMOS and calibrated them with experimental measurements. Since low-temperature operation leads to an exponential decrease in the leakage current of the transistors, we further tune the threshold voltage of the devices to achieve iso-leakage. In this article, we present inverter static and dynamic characteristics and multiple ring oscillator (RO) structures. The simulation study shows that we can achieve 28% (FO4-RO) – 59% (NAND3-RO) higher performance under iso-<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {DD}}$ </tex-math></inline-formula> scenario and up to 90% improvement in the energy-delay product (EDP) under iso-overdrive scenario at 6 K compared to room temperature.https://ieeexplore.ieee.org/document/9627705/Berkeley Short-channel IGFET Model (BSIM)4cryogenic CMOS (Cryo-CMOS)ring oscillators (ROs)standard cellsstatic characteristicsthreshold voltage |
| spellingShingle | Rakshith Saligram Wriddhi Chakraborty Ningyuan Cao Yu Cao Suman Datta Arijit Raychowdhury Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Berkeley Short-channel IGFET Model (BSIM)4 cryogenic CMOS (Cryo-CMOS) ring oscillators (ROs) standard cells static characteristics threshold voltage |
| title | Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models |
| title_full | Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models |
| title_fullStr | Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models |
| title_full_unstemmed | Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models |
| title_short | Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models |
| title_sort | power performance analysis of digital standard cells for 28 nm bulk cmos at cryogenic temperature using bsim models |
| topic | Berkeley Short-channel IGFET Model (BSIM)4 cryogenic CMOS (Cryo-CMOS) ring oscillators (ROs) standard cells static characteristics threshold voltage |
| url | https://ieeexplore.ieee.org/document/9627705/ |
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