Full utilization, fairness, and access delay on high speed slotted bus networks

Full utilization, fairness, and access delay on high speed slotted bus networks

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.

Bibliographic Details
Main Author: Chiu, Angela Lan
Other Authors: Robert G. Gallager.
Format: Thesis
Language:eng
Published: Massachusetts Institute of Technology 2005
Subjects:
Electrical Engineering and Computer Science
Online Access:http://hdl.handle.net/1721.1/10264

Internet

http://hdl.handle.net/1721.1/10264

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