Nanofabrication of arrays of silicon field emitters with vertical silicon nanowire current limiters and self-aligned gates
We developed a fabrication process for embedding a dense array (10⁸cm⁻²) of high-aspect-ratio silicon nanowires (200 nm diameter and 10 μm tall) in a dielectric matrix and then structured/exposed the tips of the nanowires to form self-aligned gate field emitter arrays using chemical mechanical polis...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
| Published: |
IOP Publishing
2017
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| Online Access: | http://hdl.handle.net/1721.1/110709 https://orcid.org/0000-0003-3946-2862 https://orcid.org/0000-0003-3001-9223 |
| Summary: | We developed a fabrication process for embedding a dense array (10⁸cm⁻²) of high-aspect-ratio silicon nanowires (200 nm diameter and 10 μm tall) in a dielectric matrix and then structured/exposed the tips of the nanowires to form self-aligned gate field emitter arrays using chemical mechanical polishing (CMP). Using this structure, we demonstrated a high current density (100 A cm⁻²), uniform, and long lifetime (>100 h) silicon field emitter array architecture in which the current emitted by each tip is regulated by the silicon nanowire current limiter connected in series with the tip. Using the current voltage characteristics and with the aid of numerical device models, we estimated the tip radius of our field emission arrays to be ≈4.8 nm, as consistent with the tip radius measured using a scanning electron microscope (SEM). |
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