A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs

A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs

We have developed a scalable gate-last process to fabricate self-aligned InGaAs FinFETs that relies on extensive use of dry etch. The process involves F-based dry etching of refractory metal ohmic contacts that are formed early in the process. The fins are etched in a novel inductive coupled plasma...

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Bibliographic Details
Main Authors: Vardi, Assaf, Lin, Jian, Lu, W., Zhao, X., Fernando Saavedra, Amalia Luisa, del Alamo, Jesus A
Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Format: Article
Language:English
Published: Institute of Electrical and Electronics Engineers (IEEE) 2019
Online Access:https://hdl.handle.net/1721.1/121163

Internet

https://hdl.handle.net/1721.1/121163

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