A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs
We have developed a scalable gate-last process to fabricate self-aligned InGaAs FinFETs that relies on extensive use of dry etch. The process involves F-based dry etching of refractory metal ohmic contacts that are formed early in the process. The fins are etched in a novel inductive coupled plasma...
| Main Authors: | , , , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
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Institute of Electrical and Electronics Engineers (IEEE)
2019
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| Online Access: | https://hdl.handle.net/1721.1/121163 |
| _version_ | 1826208224452280320 |
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| author | Vardi, Assaf Lin, Jian Lu, W. Zhao, X. Fernando Saavedra, Amalia Luisa del Alamo, Jesus A |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Vardi, Assaf Lin, Jian Lu, W. Zhao, X. Fernando Saavedra, Amalia Luisa del Alamo, Jesus A |
| author_sort | Vardi, Assaf |
| collection | MIT |
| description | We have developed a scalable gate-last process to fabricate self-aligned InGaAs FinFETs that relies on extensive use of dry etch. The process involves F-based dry etching of refractory metal ohmic contacts that are formed early in the process. The fins are etched in a novel inductive coupled plasma process using BCl[subscript 3]/SiCl[subscript 4]/Ar. High aspect ratio fins with smooth sidewalls are obtained. To further improve the quality of the sidewalls and shrink the fin width, digital etch is used. Through this process flow, we have demonstrated FinFETs with L[subscript g] = 20 nm and fin width as narrow as 7 nm with high yield. Good electrostatic characteristics are obtained in a wide range of device dimensions. In devices with 7 nm fin width, record channel aspect ratio, and transconductance per unit footprint are obtained. |
| first_indexed | 2024-09-23T14:02:29Z |
| format | Article |
| id | mit-1721.1/121163 |
| institution | Massachusetts Institute of Technology |
| language | English |
| last_indexed | 2024-09-23T14:02:29Z |
| publishDate | 2019 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/1211632022-09-28T17:55:43Z A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs Vardi, Assaf Lin, Jian Lu, W. Zhao, X. Fernando Saavedra, Amalia Luisa del Alamo, Jesus A Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science We have developed a scalable gate-last process to fabricate self-aligned InGaAs FinFETs that relies on extensive use of dry etch. The process involves F-based dry etching of refractory metal ohmic contacts that are formed early in the process. The fins are etched in a novel inductive coupled plasma process using BCl[subscript 3]/SiCl[subscript 4]/Ar. High aspect ratio fins with smooth sidewalls are obtained. To further improve the quality of the sidewalls and shrink the fin width, digital etch is used. Through this process flow, we have demonstrated FinFETs with L[subscript g] = 20 nm and fin width as narrow as 7 nm with high yield. Good electrostatic characteristics are obtained in a wide range of device dimensions. In devices with 7 nm fin width, record channel aspect ratio, and transconductance per unit footprint are obtained. United States. Defense Threat Reduction Agency (Grant HDTRA1-14-1-0057) National Science Foundation (U.S.) (Grant E3S-STC-0939514) 2019-05-20T16:40:56Z 2019-05-20T16:40:56Z 2017-11 2019-05-17T15:33:04Z Article http://purl.org/eprint/type/JournalArticle 0894-6507 1558-2345 https://hdl.handle.net/1721.1/121163 Vardi, A. et al. "A Si Compatible Fabriacaton Process for Scaled Self-Aligned InGaAs FinFets." IEEE Transactions on Semiconductor Manufacturing, 30, 4 (November 2017): 468 - 474 © 2017 IEEE en 10.1109/tsm.2017.2753141 IEEE Transactions on Semiconductor Manufacturing Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Institute of Electrical and Electronics Engineers (IEEE) MIT web domain |
| spellingShingle | Vardi, Assaf Lin, Jian Lu, W. Zhao, X. Fernando Saavedra, Amalia Luisa del Alamo, Jesus A A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs |
| title | A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs |
| title_full | A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs |
| title_fullStr | A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs |
| title_full_unstemmed | A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs |
| title_short | A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs |
| title_sort | si compatible fabrication process for scaled self aligned ingaas finfets |
| url | https://hdl.handle.net/1721.1/121163 |
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