Leveraging latency-insensitivity to ease multiple FPGA design
Traditionally, hardware designs partitioned across multiple FPGAs have had low performance due to the inefficiency of maintaining cycle-by-cycle timing among discrete FPGAs. In this paper, we present a mechanism by which complex designs may be efficiently and automatically partitioned among multiple...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
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Association for Computing Machinery (ACM)
2019
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| Online Access: | https://hdl.handle.net/1721.1/121446 |
| _version_ | 1811077422749057024 |
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| author | Fleming, Kermin Elliott Pellauer, Michael Arvind, Arvind Emer, Joel S |
| author2 | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory |
| author_facet | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory Fleming, Kermin Elliott Pellauer, Michael Arvind, Arvind Emer, Joel S |
| author_sort | Fleming, Kermin Elliott |
| collection | MIT |
| description | Traditionally, hardware designs partitioned across multiple FPGAs have had low performance due to the inefficiency of maintaining cycle-by-cycle timing among discrete FPGAs. In this paper, we present a mechanism by which complex designs may be efficiently and automatically partitioned among multiple FPGAs using explicitly programmed latency-insensitive links. We describe the automatic synthesis of an area efficient, high performance network for routing these inter-FPGA links. By mapping a diverse set of large research prototypes onto a multiple FPGA platform, we demonstrate that our tool obtains significant gains in design feasibility, compilation time, and even wall-clock performance. |
| first_indexed | 2024-09-23T10:42:46Z |
| format | Article |
| id | mit-1721.1/121446 |
| institution | Massachusetts Institute of Technology |
| language | English |
| last_indexed | 2024-09-23T10:42:46Z |
| publishDate | 2019 |
| publisher | Association for Computing Machinery (ACM) |
| record_format | dspace |
| spelling | mit-1721.1/1214462022-09-30T22:28:28Z Leveraging latency-insensitivity to ease multiple FPGA design Fleming, Kermin Elliott Pellauer, Michael Arvind, Arvind Emer, Joel S Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory Traditionally, hardware designs partitioned across multiple FPGAs have had low performance due to the inefficiency of maintaining cycle-by-cycle timing among discrete FPGAs. In this paper, we present a mechanism by which complex designs may be efficiently and automatically partitioned among multiple FPGAs using explicitly programmed latency-insensitive links. We describe the automatic synthesis of an area efficient, high performance network for routing these inter-FPGA links. By mapping a diverse set of large research prototypes onto a multiple FPGA platform, we demonstrate that our tool obtains significant gains in design feasibility, compilation time, and even wall-clock performance. Intel Corporation. Graduate Fellowship 2019-06-28T13:27:36Z 2019-06-28T13:27:36Z 2012-02 2019-06-27T16:51:16Z Article http://purl.org/eprint/type/ConferencePaper 978-1-4503-1155-7 https://hdl.handle.net/1721.1/121446 Fleming, Kermin, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind and Joel Emer. "Leveraging latency-insensitivity to ease multiple FPGA design." In Proceeding FPGA '12 Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays, Monterey, California, USA, February 22-24, 2012, pages 175-184. en 10.1145/2145694.2145725 Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Association for Computing Machinery (ACM) MIT web domain |
| spellingShingle | Fleming, Kermin Elliott Pellauer, Michael Arvind, Arvind Emer, Joel S Leveraging latency-insensitivity to ease multiple FPGA design |
| title | Leveraging latency-insensitivity to ease multiple FPGA design |
| title_full | Leveraging latency-insensitivity to ease multiple FPGA design |
| title_fullStr | Leveraging latency-insensitivity to ease multiple FPGA design |
| title_full_unstemmed | Leveraging latency-insensitivity to ease multiple FPGA design |
| title_short | Leveraging latency-insensitivity to ease multiple FPGA design |
| title_sort | leveraging latency insensitivity to ease multiple fpga design |
| url | https://hdl.handle.net/1721.1/121446 |
| work_keys_str_mv | AT flemingkerminelliott leveraginglatencyinsensitivitytoeasemultiplefpgadesign AT pellauermichael leveraginglatencyinsensitivitytoeasemultiplefpgadesign AT arvindarvind leveraginglatencyinsensitivitytoeasemultiplefpgadesign AT emerjoels leveraginglatencyinsensitivitytoeasemultiplefpgadesign |