Leveraging latency-insensitivity to ease multiple FPGA design
Traditionally, hardware designs partitioned across multiple FPGAs have had low performance due to the inefficiency of maintaining cycle-by-cycle timing among discrete FPGAs. In this paper, we present a mechanism by which complex designs may be efficiently and automatically partitioned among multiple...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
Association for Computing Machinery (ACM)
2019
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| Online Access: | https://hdl.handle.net/1721.1/121446 |