Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process
The integration of III-V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing hand...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
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Japan Society of Applied Physics
2020
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| Online Access: | https://hdl.handle.net/1721.1/124355 |
| _version_ | 1811075169994670080 |
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| author | Lee, Kwang Hong Bao, Shuyu Zhang, Li Kohen, David Fitzgerald, Eugene A Tan, Chuan Seng |
| author2 | Singapore-MIT Alliance in Research and Technology (SMART) |
| author_facet | Singapore-MIT Alliance in Research and Technology (SMART) Lee, Kwang Hong Bao, Shuyu Zhang, Li Kohen, David Fitzgerald, Eugene A Tan, Chuan Seng |
| author_sort | Lee, Kwang Hong |
| collection | MIT |
| description | The integration of III-V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing handle wafer. After that, the Si from the GaAs/Ge/Si substrate is removed. The GaN/Si substrate is then bonded to the SOI-GaAs/Ge-containing handle wafer. Finally, the handle wafer is released to realize the SOI-GaAs/Ge/GaN/Si hybrid structure on a Si substrate. By this method, the functionalities of the materials used can be combined on a single Si platform. |
| first_indexed | 2024-09-23T10:01:56Z |
| format | Article |
| id | mit-1721.1/124355 |
| institution | Massachusetts Institute of Technology |
| language | English |
| last_indexed | 2024-09-23T10:01:56Z |
| publishDate | 2020 |
| publisher | Japan Society of Applied Physics |
| record_format | dspace |
| spelling | mit-1721.1/1243552022-10-25T04:44:01Z Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process Lee, Kwang Hong Bao, Shuyu Zhang, Li Kohen, David Fitzgerald, Eugene A Tan, Chuan Seng Singapore-MIT Alliance in Research and Technology (SMART) Massachusetts Institute of Technology. Department of Materials Science and Engineering The integration of III-V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing handle wafer. After that, the Si from the GaAs/Ge/Si substrate is removed. The GaN/Si substrate is then bonded to the SOI-GaAs/Ge-containing handle wafer. Finally, the handle wafer is released to realize the SOI-GaAs/Ge/GaN/Si hybrid structure on a Si substrate. By this method, the functionalities of the materials used can be combined on a single Si platform. National Research Foundation Singapore 2020-03-26T14:42:06Z 2020-03-26T14:42:06Z 2016-07 2016-04 2019-09-18T17:04:37Z Article http://purl.org/eprint/type/JournalArticle 1882-0778 1882-0786 https://hdl.handle.net/1721.1/124355 Lee, Kwang Hong et al. "Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process." Applied Physics Express, 9, 8 (July 2016) © 2016 The Japan Society of Applied Physics. en http://dx.doi.org/10.7567/apex.9.086501 Applied Physics Express Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Japan Society of Applied Physics other univ website |
| spellingShingle | Lee, Kwang Hong Bao, Shuyu Zhang, Li Kohen, David Fitzgerald, Eugene A Tan, Chuan Seng Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process |
| title | Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process |
| title_full | Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process |
| title_fullStr | Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process |
| title_full_unstemmed | Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process |
| title_short | Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process |
| title_sort | integration of gaas gan and si cmos on a common 200 mm si substrate through multilayer transfer process |
| url | https://hdl.handle.net/1721.1/124355 |
| work_keys_str_mv | AT leekwanghong integrationofgaasganandsicmosonacommon200mmsisubstratethroughmultilayertransferprocess AT baoshuyu integrationofgaasganandsicmosonacommon200mmsisubstratethroughmultilayertransferprocess AT zhangli integrationofgaasganandsicmosonacommon200mmsisubstratethroughmultilayertransferprocess AT kohendavid integrationofgaasganandsicmosonacommon200mmsisubstratethroughmultilayertransferprocess AT fitzgeraldeugenea integrationofgaasganandsicmosonacommon200mmsisubstratethroughmultilayertransferprocess AT tanchuanseng integrationofgaasganandsicmosonacommon200mmsisubstratethroughmultilayertransferprocess |