Cimple: instruction and memory level parallelism: a DSL for uncovering ILP and MLP
Modern out-of-order processors have increased capacity to exploit instruction level parallelism (ILP) and memory level parallelism (MLP), e.g., by using wide superscalar pipelines and vector execution units, as well as deep buffers for inflight memory requests. These resources, however, often exhibi...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
Association of Computing Machinery
2020
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| Online Access: | https://hdl.handle.net/1721.1/125080 |