Sub-Thermal Subthreshold Characteristics in Top–Down InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs
This letter demonstrates top-down InGaAs/InAs heterojunction vertical nanowire tunnel FETs with sub-thermal subthreshold characteristics over two orders of magnitude of current. A minimal subthreshold swing of 53 mV/decade at V[subscript ds] = 0.3 V has been obtained at room temperature. An I[subscr...
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Institute of Electrical and Electronics Engineers (IEEE)
2020
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| Online Access: | https://hdl.handle.net/1721.1/126168 |
| _version_ | 1826196618495393792 |
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| author | Zhao, Xin Vardi, Alon del Alamo, Jesus A |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Zhao, Xin Vardi, Alon del Alamo, Jesus A |
| author_sort | Zhao, Xin |
| collection | MIT |
| description | This letter demonstrates top-down InGaAs/InAs heterojunction vertical nanowire tunnel FETs with sub-thermal subthreshold characteristics over two orders of magnitude of current. A minimal subthreshold swing of 53 mV/decade at V[subscript ds] = 0.3 V has been obtained at room temperature. An I[subscript 60] (defined as the highest current level where the subthreshold characteristics exhibit a transition from sub- to super-60 mV/decade behavior) of 4.3 nA/μm has been achieved at V s = 0.3 V. Compared with an earlier device generation, much reduced temperature dependence of the subthreshold characteristics is observed in this letter. The major difference between the two device generations is the drastically reduced interface trap density, evidenced by the improvement in the subthreshold swing of InGaAs vertical nanowire MOSFETs fabricated at the same time. This result suggests oxide-semiconductor interface trap-assisted tunnelling the main leakage mechanism in III-V TFETs fabricated by our process. The improvement in the interface quality has been enabled by improved gate oxide deposition and post-deposition treatment. |
| first_indexed | 2024-09-23T10:30:56Z |
| format | Article |
| id | mit-1721.1/126168 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T10:30:56Z |
| publishDate | 2020 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/1261682022-09-30T21:34:54Z Sub-Thermal Subthreshold Characteristics in Top–Down InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs Zhao, Xin Vardi, Alon del Alamo, Jesus A Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science This letter demonstrates top-down InGaAs/InAs heterojunction vertical nanowire tunnel FETs with sub-thermal subthreshold characteristics over two orders of magnitude of current. A minimal subthreshold swing of 53 mV/decade at V[subscript ds] = 0.3 V has been obtained at room temperature. An I[subscript 60] (defined as the highest current level where the subthreshold characteristics exhibit a transition from sub- to super-60 mV/decade behavior) of 4.3 nA/μm has been achieved at V s = 0.3 V. Compared with an earlier device generation, much reduced temperature dependence of the subthreshold characteristics is observed in this letter. The major difference between the two device generations is the drastically reduced interface trap density, evidenced by the improvement in the subthreshold swing of InGaAs vertical nanowire MOSFETs fabricated at the same time. This result suggests oxide-semiconductor interface trap-assisted tunnelling the main leakage mechanism in III-V TFETs fabricated by our process. The improvement in the interface quality has been enabled by improved gate oxide deposition and post-deposition treatment. 2020-07-14T02:21:48Z 2020-07-14T02:21:48Z 2017-05 Article http://purl.org/eprint/type/JournalArticle 0741-3106 1558-0563 https://hdl.handle.net/1721.1/126168 Zhao, Xin et al. "Sub-Thermal Subthreshold Characteristics in Top–Down InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs." IEEE Electron Device Letters 38, 7 (July 2017): 855 - 858 © 2017 IEEE http://dx.doi.org/10.1109/led.2017.2702612 IEEE Electron Device Letters Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Institute of Electrical and Electronics Engineers (IEEE) Prof. del Alamo via Phoebe Ayers |
| spellingShingle | Zhao, Xin Vardi, Alon del Alamo, Jesus A Sub-Thermal Subthreshold Characteristics in Top–Down InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs |
| title | Sub-Thermal Subthreshold Characteristics in Top–Down InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs |
| title_full | Sub-Thermal Subthreshold Characteristics in Top–Down InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs |
| title_fullStr | Sub-Thermal Subthreshold Characteristics in Top–Down InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs |
| title_full_unstemmed | Sub-Thermal Subthreshold Characteristics in Top–Down InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs |
| title_short | Sub-Thermal Subthreshold Characteristics in Top–Down InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs |
| title_sort | sub thermal subthreshold characteristics in top down ingaas inas heterojunction vertical nanowire tunnel fets |
| url | https://hdl.handle.net/1721.1/126168 |
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