Deep sub-micron stud-via technology for superconductor VLSI circuits

Deep sub-micron stud-via technology for superconductor VLSI circuits

A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of single Nb wiring lay...

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Bibliographic Details
Main Authors: Tolpygo, Sergey K., Bolkhovsky, Vladimir, Weir, Terence J., Johnson, Leonard M., Oliver, William D, Gouker, Mark A.
Other Authors: Lincoln Laboratory
Format: Article
Language:English
Published: IOP Publishing 2021
Online Access:https://hdl.handle.net/1721.1/130513

Internet

https://hdl.handle.net/1721.1/130513

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