Deep sub-micron stud-via technology for superconductor VLSI circuits
A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of single Nb wiring lay...
Main Authors: | , , , , , |
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Other Authors: | |
Format: | Article |
Language: | English |
Published: |
IOP Publishing
2021
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Online Access: | https://hdl.handle.net/1721.1/130513 |