Reverse Engineering the Intel Cascade Lake Mesh Interconnect
The rising core counts of multicore processors have driven the move to more scalable on-chip networks to allow for efficient communication between the cores, memory subsystem, and other processor peripherals. Intel’s latest line of Scalable processors introduced the mesh interconnect in the form of...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis |
| Published: |
Massachusetts Institute of Technology
2022
|
| Online Access: | https://hdl.handle.net/1721.1/143928 |