A Survey of Algorithms for Integrating Wafer-scale Systolic Arrays
VLSI technologists are fast developing wafer-scale integration. Rather than partitioning a silicon wafer into chips as is usually done, the idea behind wafer-scale integration is to assemble an entire system (or network of chips) on a single wafer, thus avoiding the costs and performance loss associ...
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| Published: |
2023
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| Online Access: | https://hdl.handle.net/1721.1/149111 |