Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators
Existing FPGA-based logic emulators suffer from limited inter-chip communication bandwidth, resulting in low gate utilization (10 20 percent). This resource imbalance increases the number of chips needed to emulate a particular logic design and thereby decreases emulation speed, since signals must c...
| Main Authors: | , , |
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| Published: |
2023
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| Online Access: | https://hdl.handle.net/1721.1/149212 |