Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators
Existing FPGA-based logic emulators suffer from limited inter-chip communication bandwidth, resulting in low gate utilization (10 20 percent). This resource imbalance increases the number of chips needed to emulate a particular logic design and thereby decreases emulation speed, since signals must c...
| Main Authors: | , , |
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| Published: |
2023
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| Online Access: | https://hdl.handle.net/1721.1/149212 |
| _version_ | 1811097735028277248 |
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| author | Babb, Jonathan Tessier, Russell Agarwal, Anant |
| author_facet | Babb, Jonathan Tessier, Russell Agarwal, Anant |
| author_sort | Babb, Jonathan |
| collection | MIT |
| description | Existing FPGA-based logic emulators suffer from limited inter-chip communication bandwidth, resulting in low gate utilization (10 20 percent). This resource imbalance increases the number of chips needed to emulate a particular logic design and thereby decreases emulation speed, since signals must cross more chip boundaries. Current emulators only use a fraction of potential communication bandwidth because they dedicate each FPGA pin (physical wire) to a single emulated signal (logical wire). These logical wires are not active simultaneously are only switched at emulation clock speeds. |
| first_indexed | 2024-09-23T17:04:06Z |
| id | mit-1721.1/149212 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T17:04:06Z |
| publishDate | 2023 |
| record_format | dspace |
| spelling | mit-1721.1/1492122023-03-30T03:01:29Z Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators Babb, Jonathan Tessier, Russell Agarwal, Anant Existing FPGA-based logic emulators suffer from limited inter-chip communication bandwidth, resulting in low gate utilization (10 20 percent). This resource imbalance increases the number of chips needed to emulate a particular logic design and thereby decreases emulation speed, since signals must cross more chip boundaries. Current emulators only use a fraction of potential communication bandwidth because they dedicate each FPGA pin (physical wire) to a single emulated signal (logical wire). These logical wires are not active simultaneously are only switched at emulation clock speeds. 2023-03-29T14:37:13Z 2023-03-29T14:37:13Z 1992-11 https://hdl.handle.net/1721.1/149212 MIT-LCS-TM-491 application/pdf |
| spellingShingle | Babb, Jonathan Tessier, Russell Agarwal, Anant Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators |
| title | Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators |
| title_full | Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators |
| title_fullStr | Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators |
| title_full_unstemmed | Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators |
| title_short | Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators |
| title_sort | virtual wires overcoming pin limitations in fpga based logic emulators |
| url | https://hdl.handle.net/1721.1/149212 |
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