Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators

Existing FPGA-based logic emulators suffer from limited inter-chip communication bandwidth, resulting in low gate utilization (10 20 percent). This resource imbalance increases the number of chips needed to emulate a particular logic design and thereby decreases emulation speed, since signals must c...

Ausführliche Beschreibung

Bibliographische Detailangaben
Hauptverfasser: Babb, Jonathan, Tessier, Russell, Agarwal, Anant
Veröffentlicht: 2023
Online Zugang:https://hdl.handle.net/1721.1/149212