How to Build Scalable On-Chip ILP Networks for a Decentralized Architecture
The era of billion transistors-on-a-chip is creating a completely different set of design constraints, forcing radically new microprocessor archiecture designs. This paper examines a few of the possible microarchitectures that are capable of obtaining scalable ILP performance. First, we observe that...
| Main Authors: | , , , , |
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| Published: |
2023
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| Online Access: | https://hdl.handle.net/1721.1/149317 |