How to Build Scalable On-Chip ILP Networks for a Decentralized Architecture
The era of billion transistors-on-a-chip is creating a completely different set of design constraints, forcing radically new microprocessor archiecture designs. This paper examines a few of the possible microarchitectures that are capable of obtaining scalable ILP performance. First, we observe that...
| Main Authors: | , , , , |
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| Published: |
2023
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| Online Access: | https://hdl.handle.net/1721.1/149317 |
| _version_ | 1811088281027215360 |
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| author | Taylor, Michael Bedford Lee, Walter Frank, Matthew Amarasinghe, Saman Agarwal, Anant |
| author_facet | Taylor, Michael Bedford Lee, Walter Frank, Matthew Amarasinghe, Saman Agarwal, Anant |
| author_sort | Taylor, Michael Bedford |
| collection | MIT |
| description | The era of billion transistors-on-a-chip is creating a completely different set of design constraints, forcing radically new microprocessor archiecture designs. This paper examines a few of the possible microarchitectures that are capable of obtaining scalable ILP performance. First, we observe that the network that interconnects the processing elements is the critical design point in the microarchitecture. Next, we characterize four fundamental properties that have to be satisfied by the interconnection network. Next, we provide case studies of two different networks that satisfy these properties. Finally, a detailed evaluation of these networks is presented to highlight the scalability and performance of these microarchitectures. We show that by using compile time information, we can build simpler networks and use them efficiently. |
| first_indexed | 2024-09-23T13:59:17Z |
| id | mit-1721.1/149317 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T13:59:17Z |
| publishDate | 2023 |
| record_format | dspace |
| spelling | mit-1721.1/1493172023-03-30T03:33:00Z How to Build Scalable On-Chip ILP Networks for a Decentralized Architecture Taylor, Michael Bedford Lee, Walter Frank, Matthew Amarasinghe, Saman Agarwal, Anant The era of billion transistors-on-a-chip is creating a completely different set of design constraints, forcing radically new microprocessor archiecture designs. This paper examines a few of the possible microarchitectures that are capable of obtaining scalable ILP performance. First, we observe that the network that interconnects the processing elements is the critical design point in the microarchitecture. Next, we characterize four fundamental properties that have to be satisfied by the interconnection network. Next, we provide case studies of two different networks that satisfy these properties. Finally, a detailed evaluation of these networks is presented to highlight the scalability and performance of these microarchitectures. We show that by using compile time information, we can build simpler networks and use them efficiently. 2023-03-29T14:42:44Z 2023-03-29T14:42:44Z 2000-04 https://hdl.handle.net/1721.1/149317 MIT-LCS-TM-628 application/pdf |
| spellingShingle | Taylor, Michael Bedford Lee, Walter Frank, Matthew Amarasinghe, Saman Agarwal, Anant How to Build Scalable On-Chip ILP Networks for a Decentralized Architecture |
| title | How to Build Scalable On-Chip ILP Networks for a Decentralized Architecture |
| title_full | How to Build Scalable On-Chip ILP Networks for a Decentralized Architecture |
| title_fullStr | How to Build Scalable On-Chip ILP Networks for a Decentralized Architecture |
| title_full_unstemmed | How to Build Scalable On-Chip ILP Networks for a Decentralized Architecture |
| title_short | How to Build Scalable On-Chip ILP Networks for a Decentralized Architecture |
| title_sort | how to build scalable on chip ilp networks for a decentralized architecture |
| url | https://hdl.handle.net/1721.1/149317 |
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