Models and Data Structures for Digital Logic Simulation

A digital logic simulation system is proposed for design verification. Logic to be simulated is specified with a high level register transfer design language, and the simulation system operates on-line on a large time-shared computer. The problem of selecting adequate circuit and signal models fo...

Disgrifiad llawn

Manylion Llyfryddiaeth
Prif Awdur: Smith, Donald Leigh
Awduron Eraill: Dennis, Jack B.
Cyhoeddwyd: 2023
Mynediad Ar-lein:https://hdl.handle.net/1721.1/149353