Models and Data Structures for Digital Logic Simulation
A digital logic simulation system is proposed for design verification. Logic to be simulated is specified with a high level register transfer design language, and the simulation system operates on-line on a large time-shared computer. The problem of selecting adequate circuit and signal models fo...
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2023
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| Online Access: | https://hdl.handle.net/1721.1/149353 |
| Summary: | A digital logic simulation system is proposed for design verification. Logic to be simulated is specified with a high level register transfer design language, and the simulation system operates on-line on a large time-shared computer. The problem of selecting adequate circuit and signal models for this purpose is considered. models are proposed with sufficient timing detail to allow the simulation system to detect timing errors which currently are found by manual checking or prototype. |
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