Fault Tolerance in Packet Communication Computer Archiectures
It is attractive to implement a large scale parallel processing system as a self-timed hardware system with decentralized control and to improve maintainability and availability in such a system through fault tolerance. In this thesis we show how to tolerate hardware failures in a self-timed hardwa...
Main Author: | |
---|---|
Other Authors: | |
Published: |
2023
|
Online Access: | https://hdl.handle.net/1721.1/149531 |