A Framework for Solving VSLI Graph Layout Problems
This paper introduces a new divide-and-conquer framework for VLSI graph layout. Universally close upper and lower bounds are obtained for important cost functions such as layout area and propagation delay. The framework is also effectively used to design regular and configuration layouts, to assem...
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| Published: |
2023
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| Online Access: | https://hdl.handle.net/1721.1/149581 |