Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications
This thesis presents an approach for direct and efficient synthesis of self-timed (asynchronous) control circuits from formal specifications called Signal Transition Graphs (STGs). Control circuits synthesized from this graph model are speed-independent and capable of performing concurrent operatio...
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2023
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| Online Access: | https://hdl.handle.net/1721.1/149657 |