A Silicate-Based Packaging Material for 3-D Heterogeneous Integration of Microsystems
3D heterogeneous integration (HI) and wafer-level packaging (WLP) represent the cutting edge of microelectronics design and fabrication. However, the current limitations of microelectronics packaging materials inhibit the widespread implementation of these processes, which presents an opportunity to...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis |
| Published: |
Massachusetts Institute of Technology
2023
|
| Online Access: | https://hdl.handle.net/1721.1/150254 https://orcid.org/0000-0003-4174-3399 |
| Summary: | 3D heterogeneous integration (HI) and wafer-level packaging (WLP) represent the cutting edge of microelectronics design and fabrication. However, the current limitations of microelectronics packaging materials inhibit the widespread implementation of these processes, which presents an opportunity to develop new packaging solutions using innovative materials. Building upon previous work, research on the development and characterization of an improved silicate-based packaging material for 3D HI and WLP of microelectronics with a focus on Millimeter Wave (mmWave) radio frequency (RF) applications was carried out. A sodium-free material formulation and suitability with scalable deposition techniques demonstrated compatibility with complementary metal-oxide-semiconductor (CMOS) fabrication. The material was tested and qualified for use with common microelectronics fabrication processes such as positive and negative photolithographic patterning, wet etching, and most chemical cleans (excluding highly basic chemicals). It was polishable to a surface roughness of 197 ± 29 Å, thermally stable up to 400°C, compatible with high vacuum exposure down to 1.5 ± 0.4x10⁻⁵ torr, and filled gaps with aspect ratios as high as 18.6:1 using certain techniques. The packaging material could be deposited at thicknesses ranging from single-digit microns up to several millimeters, and exhibited excellent adhesion to silicon at thicknesses below ~30 µm. Residual stress generation in films of the silicate packaging material was less than 10 MPa at thicknesses of ~20 - 90 µm. The coefficient of thermal expansion was 2.968 ± 0.054 ppm/°C from 50 - 400°C, and the dielectric constant and loss tangent were ~4 and ~0.0002 at 110 GHz. Successful fabrication of a coplanar waveguide and prototype reconstituted wafers demonstrated that the packaging material can be used to make RF devices and to enable 3D HI and WLP. |
|---|