Accelerating RTL Simulation with Hardware-Software Co-Design

Accelerating RTL Simulation with Hardware-Software Co-Design

Fast simulation of digital circuits is crucial to build modern chips. But RTL (Register-Transfer-Level) simulators are slow, as they cannot exploit multicores well. Slow simulation lengthens chip design time and makes bugs more frequent. We present ASH, a parallel architecture tailored to simulat...

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Bibliographic Details
Main Authors: Elsabbagh, Fares, Sheikhha, Shabnam, Ying, Victor, Nguyen, Quan, Emer, Joel, Sanchez, Daniel
Other Authors: Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Format: Article
Language:English
Published: ACM|56th Annual IEEE/ACM International Symposium on Microarchitecture 2024
Online Access:https://hdl.handle.net/1721.1/153269

Internet

https://hdl.handle.net/1721.1/153269

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