Accelerating RTL Simulation with Hardware-Software Co-Design
Fast simulation of digital circuits is crucial to build modern chips. But RTL (Register-Transfer-Level) simulators are slow, as they cannot exploit multicores well. Slow simulation lengthens chip design time and makes bugs more frequent. We present ASH, a parallel architecture tailored to simulat...
| Main Authors: | , , , , , |
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| 其他作者: | |
| 格式: | 文件 |
| 语言: | English |
| 出版: |
ACM|56th Annual IEEE/ACM International Symposium on Microarchitecture
2024
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| 在线阅读: | https://hdl.handle.net/1721.1/153269 |