Lab-to-Fab Monolithic 3D Integrated Carbon Nanotube Transistors: Scaling and Reliability
Conventional scaling of silicon integrated electronics can no longer yield improvements that keep pace with the increasing computing demands of abundant-data applications. Moreover, for data intensive computing applications, a majority of system energy is consumed moving data between compute and off...
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| Format: | Thesis |
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Massachusetts Institute of Technology
2024
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| Online Access: | https://hdl.handle.net/1721.1/156634 |
| _version_ | 1826203560893743104 |
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| author | Yu, Andrew C. |
| author2 | Shulaker, Max M. |
| author_facet | Shulaker, Max M. Yu, Andrew C. |
| author_sort | Yu, Andrew C. |
| collection | MIT |
| description | Conventional scaling of silicon integrated electronics can no longer yield improvements that keep pace with the increasing computing demands of abundant-data applications. Moreover, for data intensive computing applications, a majority of system energy is consumed moving data between compute and off-chip memory, which are often physically separate with limited connectivity. This is termed the “memory wall”. A promising solution to this problem is monolithic 3D integration, in which layers of compute and memory are designed and integrated together vertically in the same monolithic 3D nanosystem, connected by ultra-dense, nanoscale interconnects, referred to as interlayer vias (ILVs). This provides significant projected system-level energy-delay benefits beyond conventional 2D physical and equivalent scaling. However, conventional silicon logic and memory technologies are incompatible with such monolithic 3D integration and cannot be used to realize such 3D nanosystems.
In this thesis, I first develop, and then establish within a commercial foundry, a monolithic 3D technology using back-end-of-line (BEOL) carbon nanotube FET (CNFET) + Resistive RAM (RRAM) stack over silicon CMOS that achieves comparable memory performance (read power, write energy/latency, endurance, retention, multiple bits-per-cell capability) in the same footprint as a conventional RRAM stack using front-end-of-line (FEOL) silicon FET access transistors. This is accomplished through the following: (1) I develop the first CNFET process that is lift-off-free and can scale to advanced process technology nodes, (2) I lab-to-fab transfer and adapt this process from an academic prototype into a commercial CMOS foundry process on 200 mm wafers at a 90 nm technology node equivalent, and (3) I improve the scaling, variation, and reliability of lift-offfree BEOL CNFET to achieve iso-performance, iso-footprint, and iso-reliability BEOL memory metrics. This process is established within SkyWater Technology Foundry (90/130nm technology 3 node on 200 mm Si wafers) and an apples-to-apples comparison is made directly versus FEOL Si FET + RRAM fabricated on the same wafers, from the same foundry, at the same node.
Such BEOL CNFET + RRAM technology promises to unlock a large architecture design space with significant system-level energy-delay product (EDP) benefits vs. FEOL Si + RRAM-only designs, e.g., >5× EDP benefits for new iso-footprint, iso-memory-capacity monolithic 3D architectures uniquely enabled by new monolithic 3D physical design. In summary, this thesis experimentally implements and demonstrates foundry monolithic 3D using beyond-silicon nanotechnologies as a complementary integration path for dramatically improving system-level energy-efficiency and performance. |
| first_indexed | 2024-09-23T12:39:32Z |
| format | Thesis |
| id | mit-1721.1/156634 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T12:39:32Z |
| publishDate | 2024 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/1566342024-09-04T03:32:25Z Lab-to-Fab Monolithic 3D Integrated Carbon Nanotube Transistors: Scaling and Reliability Yu, Andrew C. Shulaker, Max M. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Conventional scaling of silicon integrated electronics can no longer yield improvements that keep pace with the increasing computing demands of abundant-data applications. Moreover, for data intensive computing applications, a majority of system energy is consumed moving data between compute and off-chip memory, which are often physically separate with limited connectivity. This is termed the “memory wall”. A promising solution to this problem is monolithic 3D integration, in which layers of compute and memory are designed and integrated together vertically in the same monolithic 3D nanosystem, connected by ultra-dense, nanoscale interconnects, referred to as interlayer vias (ILVs). This provides significant projected system-level energy-delay benefits beyond conventional 2D physical and equivalent scaling. However, conventional silicon logic and memory technologies are incompatible with such monolithic 3D integration and cannot be used to realize such 3D nanosystems. In this thesis, I first develop, and then establish within a commercial foundry, a monolithic 3D technology using back-end-of-line (BEOL) carbon nanotube FET (CNFET) + Resistive RAM (RRAM) stack over silicon CMOS that achieves comparable memory performance (read power, write energy/latency, endurance, retention, multiple bits-per-cell capability) in the same footprint as a conventional RRAM stack using front-end-of-line (FEOL) silicon FET access transistors. This is accomplished through the following: (1) I develop the first CNFET process that is lift-off-free and can scale to advanced process technology nodes, (2) I lab-to-fab transfer and adapt this process from an academic prototype into a commercial CMOS foundry process on 200 mm wafers at a 90 nm technology node equivalent, and (3) I improve the scaling, variation, and reliability of lift-offfree BEOL CNFET to achieve iso-performance, iso-footprint, and iso-reliability BEOL memory metrics. This process is established within SkyWater Technology Foundry (90/130nm technology 3 node on 200 mm Si wafers) and an apples-to-apples comparison is made directly versus FEOL Si FET + RRAM fabricated on the same wafers, from the same foundry, at the same node. Such BEOL CNFET + RRAM technology promises to unlock a large architecture design space with significant system-level energy-delay product (EDP) benefits vs. FEOL Si + RRAM-only designs, e.g., >5× EDP benefits for new iso-footprint, iso-memory-capacity monolithic 3D architectures uniquely enabled by new monolithic 3D physical design. In summary, this thesis experimentally implements and demonstrates foundry monolithic 3D using beyond-silicon nanotechnologies as a complementary integration path for dramatically improving system-level energy-efficiency and performance. Ph.D. 2024-09-03T21:13:32Z 2024-09-03T21:13:32Z 2024-05 2024-07-10T13:02:26.099Z Thesis https://hdl.handle.net/1721.1/156634 In Copyright - Educational Use Permitted Copyright retained by author(s) https://rightsstatements.org/page/InC-EDU/1.0/ application/pdf Massachusetts Institute of Technology |
| spellingShingle | Yu, Andrew C. Lab-to-Fab Monolithic 3D Integrated Carbon Nanotube Transistors: Scaling and Reliability |
| title | Lab-to-Fab Monolithic 3D Integrated Carbon Nanotube Transistors: Scaling and Reliability |
| title_full | Lab-to-Fab Monolithic 3D Integrated Carbon Nanotube Transistors: Scaling and Reliability |
| title_fullStr | Lab-to-Fab Monolithic 3D Integrated Carbon Nanotube Transistors: Scaling and Reliability |
| title_full_unstemmed | Lab-to-Fab Monolithic 3D Integrated Carbon Nanotube Transistors: Scaling and Reliability |
| title_short | Lab-to-Fab Monolithic 3D Integrated Carbon Nanotube Transistors: Scaling and Reliability |
| title_sort | lab to fab monolithic 3d integrated carbon nanotube transistors scaling and reliability |
| url | https://hdl.handle.net/1721.1/156634 |
| work_keys_str_mv | AT yuandrewc labtofabmonolithic3dintegratedcarbonnanotubetransistorsscalingandreliability |