Pattern-placement-error detection for spatial-phase-locked e-beam lithography (SPLEBL)

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.

Bibliographic Details
Main Author: Caramana, Cynthia L. (Cynthia Louise), 1978-
Other Authors: Henry I. Smith.
Format: Thesis
Language:en_US
Published: Massachusetts Institute of Technology 2005
Subjects:
Online Access:http://hdl.handle.net/1721.1/28490
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author Caramana, Cynthia L. (Cynthia Louise), 1978-
author2 Henry I. Smith.
author_facet Henry I. Smith.
Caramana, Cynthia L. (Cynthia Louise), 1978-
author_sort Caramana, Cynthia L. (Cynthia Louise), 1978-
collection MIT
description Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
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spelling mit-1721.1/284902019-04-10T23:03:39Z Pattern-placement-error detection for spatial-phase-locked e-beam lithography (SPLEBL) Pattern-placement-error detection for SPLEBL Caramana, Cynthia L. (Cynthia Louise), 1978- Henry I. Smith. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004. Includes bibliographical references (p. 107-109). Spatial-phase-locked electron-beam lithography (SPLEBL) is a new paradigm for scanning electron-beam lithography (SEBL) that permits nanometer-level pattern placement accuracy. Unlike conventional SEBL systems which run in an open-loop fashion, SPLEBL uses continuous feedback to directly monitor and correct the beam's position, eliminating the need for expensive shielding equipment and costly isolation techniques. When compared to the most advanced and sophisticated SEBL systems, SPLEBL exceeds all of them in the areas of pattern-placement accuracy and affordability. However, much improvement is needed to increase the throughput of SPLEBL to a level on par with its commercial counterparts. As SPLEBL is further optimized for throughput and affordability, the placement-error detection and correction subsystem will need to be upgraded with a custom hardware solution. The work presented in this thesis describes the design of an efficient error detection and correction mechanism for SPLEBL and how it could be implemented as a digital circuit. An error-detection algorithm, well suited for digital hardware, has been developed and characterized. A digital circuit design to implement the algorithm has been created, optimized, and verified using the MathWorks SimulinkTM and the Xilinx System GeneratorTM hardware design tools. by Cynthia L. Caramana. S.M. 2005-09-26T20:44:09Z 2005-09-26T20:44:09Z 2004 2004 Thesis http://hdl.handle.net/1721.1/28490 57303688 en_US M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 109 p. 4015829 bytes 4028772 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology
spellingShingle Electrical Engineering and Computer Science.
Caramana, Cynthia L. (Cynthia Louise), 1978-
Pattern-placement-error detection for spatial-phase-locked e-beam lithography (SPLEBL)
title Pattern-placement-error detection for spatial-phase-locked e-beam lithography (SPLEBL)
title_full Pattern-placement-error detection for spatial-phase-locked e-beam lithography (SPLEBL)
title_fullStr Pattern-placement-error detection for spatial-phase-locked e-beam lithography (SPLEBL)
title_full_unstemmed Pattern-placement-error detection for spatial-phase-locked e-beam lithography (SPLEBL)
title_short Pattern-placement-error detection for spatial-phase-locked e-beam lithography (SPLEBL)
title_sort pattern placement error detection for spatial phase locked e beam lithography splebl
topic Electrical Engineering and Computer Science.
url http://hdl.handle.net/1721.1/28490
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