Spatial yield modeling for semiconductor wafers
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2007
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| Online Access: | http://hdl.handle.net/1721.1/37537 |
| _version_ | 1826204282944225280 |
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| author | Mirza, Agha Irtaza |
| author2 | Alvin W. Drake. |
| author_facet | Alvin W. Drake. Mirza, Agha Irtaza |
| author_sort | Mirza, Agha Irtaza |
| collection | MIT |
| description | Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995. |
| first_indexed | 2024-09-23T12:51:50Z |
| format | Thesis |
| id | mit-1721.1/37537 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T12:51:50Z |
| publishDate | 2007 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/375372019-04-11T14:18:57Z Spatial yield modeling for semiconductor wafers Mirza, Agha Irtaza Alvin W. Drake. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science Electrical Engineering and Computer Science Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995. Includes bibliographical references (p. 123-124). by Agha Irtaza Mirza. M.S. 2007-05-16T18:54:32Z 2007-05-16T18:54:32Z 1995 1995 Thesis http://hdl.handle.net/1721.1/37537 33228512 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 124 p. application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science Mirza, Agha Irtaza Spatial yield modeling for semiconductor wafers |
| title | Spatial yield modeling for semiconductor wafers |
| title_full | Spatial yield modeling for semiconductor wafers |
| title_fullStr | Spatial yield modeling for semiconductor wafers |
| title_full_unstemmed | Spatial yield modeling for semiconductor wafers |
| title_short | Spatial yield modeling for semiconductor wafers |
| title_sort | spatial yield modeling for semiconductor wafers |
| topic | Electrical Engineering and Computer Science |
| url | http://hdl.handle.net/1721.1/37537 |
| work_keys_str_mv | AT mirzaaghairtaza spatialyieldmodelingforsemiconductorwafers |