Three dimensional integration technology using copper wafer bonding
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2008
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| Online Access: | http://dspace.mit.edu/handle/1721.1/37915 http://hdl.handle.net/1721.1/37915 |
| _version_ | 1811096221867048960 |
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| author | Fan, Andy, 1976- |
| author2 | L. Rafael Reif and Akintunde Ibitayo Akinwande. |
| author_facet | L. Rafael Reif and Akintunde Ibitayo Akinwande. Fan, Andy, 1976- |
| author_sort | Fan, Andy, 1976- |
| collection | MIT |
| description | Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006. |
| first_indexed | 2024-09-23T16:40:30Z |
| format | Thesis |
| id | mit-1721.1/37915 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T16:40:30Z |
| publishDate | 2008 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/379152019-04-10T22:21:50Z Three dimensional integration technology using copper wafer bonding Fan, Andy, 1976- L. Rafael Reif and Akintunde Ibitayo Akinwande. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006. Includes bibliographical references (p. 216-219). With 3-D integration, the added vertical component could theoretically increase the device density per footprint ratio of a given chip by n-fold, provide a means of heterogeneous integration of devices fabricated from different technologies, and reduce the global RC delay to a non-factor in circuits by using smarter 3-D CAD tools for optimizing device placement. This thesis work will focus primarily on the development and realization of a viable 3-D flow fabricated within MTL. Specifically, the presentation will attempt on answering these questions in regards to 3-D: 1. What enabling technologies were needed for 3-D to work ? 2. Does it really work ? 3. Will the "3-D heat dissipation problem" prevent it from working ? 4. What applications is it good for ? Referring to the first item, a viable 3-D integration flow has been developed on both the wafer-and-die-level, and the enabling technologies were the following: Low temperature Cu-Cu thermocompression bonding, an aluminum-Cu based temporary laminate structure used stabilizing the handle wafer - SOI wafer bond, and tooling optimization of the die-die bonder setup in TRL. (cont.,) Next, nominal feasibility of the 3-D flow was demonstrated by fabricating a 21-stage and 43-stage CMOS ring oscillators, where each single CMOS inverter / buffer stage was constructed by connecting NMOS-only devices from one substrate with PMOS-only devices from a separate substrate. Proof-of-concept was accomplished when all 92 Cu-Cu bonds, 204 thru-SOI Cu damascene vias, and 56 pairs of MOSFETs communicated simultaneously to produce a 2.75 MHz (43-stage) and 5.5 MHz (21-stage) oscillators, ringing rail-to-rail at 5 V Vdd under proper Vt adjustments on the SOI-PMOS using integrated backgates. Furthermore, to combat the perceived heat dissipation problem in 3-D, this work focused on using the Cu-Cu interlayer bond as heat dissipators, with Cu planes working as flux spreaders and Cu vias as direct heat conduits. Finally, 3-D RF passive integration onto existing chips can be made feasible, under certain device performance trade-offs, by using cobalt magnetic shielding, which offers at least a -10 dB throughout 0-20 GHz, with a max isolation of -24 dB at 13 GHz, at +4 dBm reference input power. by Andy Fan. Ph.D. 2008-03-26T20:27:28Z 2008-03-26T20:27:28Z 2006 2006 Thesis http://dspace.mit.edu/handle/1721.1/37915 http://hdl.handle.net/1721.1/37915 133175288 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/37915 http://dspace.mit.edu/handle/1721.1/7582 219 p. application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Fan, Andy, 1976- Three dimensional integration technology using copper wafer bonding |
| title | Three dimensional integration technology using copper wafer bonding |
| title_full | Three dimensional integration technology using copper wafer bonding |
| title_fullStr | Three dimensional integration technology using copper wafer bonding |
| title_full_unstemmed | Three dimensional integration technology using copper wafer bonding |
| title_short | Three dimensional integration technology using copper wafer bonding |
| title_sort | three dimensional integration technology using copper wafer bonding |
| topic | Electrical Engineering and Computer Science. |
| url | http://dspace.mit.edu/handle/1721.1/37915 http://hdl.handle.net/1721.1/37915 |
| work_keys_str_mv | AT fanandy1976 threedimensionalintegrationtechnologyusingcopperwaferbonding |