A 65 nm Sub- V_{t} Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter
Aggressive supply voltage scaling to below the device threshold voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process vari...
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers
2010
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| Online Access: | http://hdl.handle.net/1721.1/52467 https://orcid.org/0000-0002-5977-2748 |
| _version_ | 1826210726712180736 |
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| author | Verma, Naveen Ramadass, Yogesh Kumar Kwong, Joyce Chandrakasan, Anantha P. |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Verma, Naveen Ramadass, Yogesh Kumar Kwong, Joyce Chandrakasan, Anantha P. |
| author_sort | Verma, Naveen |
| collection | MIT |
| description | Aggressive supply voltage scaling to below the device threshold voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process variation become more prominent at low voltages, particularly in deeply scaled technologies. This paper presents a 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV. A 16-bit microcontroller core is designed with a custom sub-threshold cell library and timing methodology to address output voltage failures and propagation delays in logic gates. A 128 kb SRAM employs an 8 T bit-cell to ensure read stability, and peripheral assist circuitry to allow sub-Vt reading and writing. The logic and SRAM function in the range of 300 mV to 600 mV, consume 27.2 pJ/cycle at the optimal V [subscript DD] of 500 mV, and 1 muW standby power at 300 mV. To supply variable voltages at these low power levels, a switched capacitor DC-DC converter is integrated on-chip and achieves above 75% efficiency while delivering between 10 muW to 250 muW of load power. |
| first_indexed | 2024-09-23T14:54:12Z |
| format | Article |
| id | mit-1721.1/52467 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T14:54:12Z |
| publishDate | 2010 |
| publisher | Institute of Electrical and Electronics Engineers |
| record_format | dspace |
| spelling | mit-1721.1/524672022-09-29T11:20:24Z A 65 nm Sub- V_{t} Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter Verma, Naveen Ramadass, Yogesh Kumar Kwong, Joyce Chandrakasan, Anantha P. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology. Microsystems Technology Laboratories Chandrakasan, Anantha P. Verma, Naveen Ramadass, Yogesh Kumar Kwong, Joyce Chandrakasan, Anantha P. Aggressive supply voltage scaling to below the device threshold voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process variation become more prominent at low voltages, particularly in deeply scaled technologies. This paper presents a 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV. A 16-bit microcontroller core is designed with a custom sub-threshold cell library and timing methodology to address output voltage failures and propagation delays in logic gates. A 128 kb SRAM employs an 8 T bit-cell to ensure read stability, and peripheral assist circuitry to allow sub-Vt reading and writing. The logic and SRAM function in the range of 300 mV to 600 mV, consume 27.2 pJ/cycle at the optimal V [subscript DD] of 500 mV, and 1 muW standby power at 300 mV. To supply variable voltages at these low power levels, a switched capacitor DC-DC converter is integrated on-chip and achieves above 75% efficiency while delivering between 10 muW to 250 muW of load power. Defense Advanced Research Projects Agency 2010-03-10T16:49:00Z 2010-03-10T16:49:00Z 2008-12 2008-08 Article http://purl.org/eprint/type/JournalArticle http://hdl.handle.net/1721.1/52467 Kwong, J. et al. “A 65 nm Sub- V_{t} Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter.” Solid-State Circuits, IEEE Journal of 44.1 (2009): 115-126. © 2008 IEEE https://orcid.org/0000-0002-5977-2748 en_US http://dx.doi.org/10.1109/jssc.2008.2007160 IEEE Journal of Solid-State Circuits Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers IEEE |
| spellingShingle | Verma, Naveen Ramadass, Yogesh Kumar Kwong, Joyce Chandrakasan, Anantha P. A 65 nm Sub- V_{t} Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter |
| title | A 65 nm Sub- V_{t} Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter |
| title_full | A 65 nm Sub- V_{t} Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter |
| title_fullStr | A 65 nm Sub- V_{t} Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter |
| title_full_unstemmed | A 65 nm Sub- V_{t} Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter |
| title_short | A 65 nm Sub- V_{t} Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter |
| title_sort | 65 nm sub v t microcontroller with integrated sram and switched capacitor dc dc converter |
| url | http://hdl.handle.net/1721.1/52467 https://orcid.org/0000-0002-5977-2748 |
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