A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS

A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS

In modern ICs, the trend of integrating more on-chip memories on a die has led SRAMs to account for a large fraction of total area and energy of a chip. Therefore, designing memories with dynamic voltage scaling (DVS) capability is important since significant active as well as leakage power savings...

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Bibliographic Details
Main Authors: Verma, Naveen, Sinangil, Mahmut Ersin, Chandrakasan, Anantha P.
Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Format: Article
Language:en_US
Published: Institute of Electrical and Electronics Engineers 2010
Subjects:
low-power SRAM design
dynamic voltage scaling
circuit reconfigurability
cache memories
Online Access:http://hdl.handle.net/1721.1/53553
https://orcid.org/0000-0002-5977-2748

Internet

http://hdl.handle.net/1721.1/53553
https://orcid.org/0000-0002-5977-2748

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